RISC-V / RISC-V Processor->32 Bits SoC Catalog

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RISC-V Catalog

Development Board (1)

RISC-V Platform (21)

RISC-V Processor (113)

RISC-V Verification (5)

ARC-V Processor IP

High-performance, Mid-range, and Ultra-low Power RISC-V Processor IP

Synopsys ARC-V Processor IP™ builds on the existing ARC processor offerings, while giving customers access to the ex...

ARC-V RHX-105 dual-issue, 32-bit multi-core RISC-V processor for real-time applications

The Synopsys ARC-V™ RHX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where real-time performance is required. The cores offer outstanding perform...

ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications

The Synopsys ARC-V™ RMX-500 series processors are optimized for use in embedded applications where power and performance efficiency are key concerns. The DSP enhanced implementation (RMX-500D) adds DS...

32 bit - Compact RISC-V Processor Core

The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and with 16 general purpose registers...

32 Bit - Embedded RISC-V Processor Core

The L31(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and has 32 general-purpose registe...

32-bit Embedded RISC-V Functional Safety Processor

The EMSA5-FS is a processor core designed for functional safety. The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing th...

Low-Power Deeply Embedded RISC-V Processor

The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core.

Single issue, embedded RISC-V core with 4-stage pipeline

The Western Digital SweRV Core™ EL2 is a single issue, RV32IMC, single-issue core with a 4-stage in-order pipeline. Like the EH1 and EH2, it supports optional instruction and data closely coupled memo...

SweRV EH1 Support Package

The SweRV EH1 Support package (SSP) contains everything needed to deploy a Western Digital SweRV EH1 core in an integrated circuit

32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN

The 32-bit N45 is an 8-stage superscalar processor that supports RISC-V specification, including (IMAFD) standard instructions, 16-bit compression instructions, and for user-level interrupts. It iss...

32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)

The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructi...

32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux

The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructi...

AndesCore N25F-SE 32-bit CPU IP

AndesCore™ N25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications. Approved based on the functional safety assignments of a Safety ...

Compact and Performance Efficiency 32-bit RISC-V Core

The AndesCore™ N225 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with small gate count, and some dual-issue ability. In addition to commonly us...

Compact High-Speed 32-bit CPU Core

AndesCore™ N25 is a 32-bit CPU IP core based on AndeStar™ V5m Instruction Set Architecture, which support RISC-V RV32IMAC extensions from the latest developments in computer architecture a...

Compact High-Speed 32-bit CPU Core with DSP

AndesCore™ D25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-MHz performance and operating at high frequencies,...

Compact High-Speed 32-bit CPU Core with DSP

Compact, Secure and Performance Efficiency 32-bit RISC-V Core

AndesCore™ D23 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5/V5e architecture for embedded applications with small gate count, and some dual-issue ability. In addition to commonly use...

Compact, Secure and Performance Efficiency 32-bit RISC-V Core

icyflex-V Low-power 32-bit RISC-V processor

The icyflex-V 32-bit processor core is based on the RV32IMC open-instruction set architecture (ISA) defined by the RISC-V foundation and, as such, is supported by standard state-of-the-art development tools (both open-source and proprietary).

Ultra Compact 32-bit RISC-V CPU Core

AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require low energy consumption and small area.

32-bit High Performance RV32GC Single/Multicore RISC System-on-Chip

The CCRV32ST-S is a synthesisable Verilog model of a high performance 32-bit RV32GC System-on-Chip.

32-bit High Performance Single/Multicore RISC Processor

The CC100-C processor is a synthesisable Verilog model of a high performance 32-bit RISC processor. The model is highly configurable, and particularly suitable for system-on-a-chip (SoC) designs. The ...

32-bit High Performance Single/Multicore RISC Processor with code compression

The CC150-C processor is a synthesisable Verilog model of a high performance 32-bit RISC processor. The model is highly configurable, and particularly suitable for system-on-a-chip (SoC) designs. The ...

32-bit High Performance Single/Multicore RISC System-on-Chip

The CC100-S is a synthesisable Verilog model of a high performance 32-bit RISC processor based System-on-Chip. The model is highly configurable and embeds a wide range of peripherals. The SoC can be e...

32-bit High Performance Single/Multicore RISC System-on-Chip with code compression

The CC150-S is a synthesisable Verilog model of a high performance 32-bit RISC processor based System-on-Chip. The model is highly configurable and embeds a wide range of peripherals. The SoC can be e...

32-bit RISC CPU for low power aplications

The 32-bit RISC CPU core features a 32x16 bit MAC capable of single cycle MAC operations, which enhances execution times of DSP instructions that are critical to DSP applications. The 32 bit datapath has been designed to minimize data, branch and structural hazard-related stalls. It can operate in five operating modes and has a shadow register bank, that provides fast context switching for high priority interrupts.

APS1V - Compact Implementation of the RISC-V RV32IMC ISA

Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. ...

APS3V - Compact Implementation of the RISC-V RV32IMC ISA

APS5V - Compact Implementation of the RISC-V RV32IMAC ISA

Compact, low-power 32-bit RISC CPU

The eSi-3200 32-bit CPU is the mid-range member in the eSi-RISC family of processor cores.

EMSA5-FS

EMSA5-FS is a 32-bit, in-order, single-issue, five-stage pipeline processor supporting the open standard RISC-V instruction set architecture (ISA).

FPS29V - Dual Issue Implementation of the RISC-V RV32IMAFC ISA

High-performance 32-bit RISC CPU

>The eSi-3250 32-bit CPU is targeted specifically for applications with high performance requiring caching, due to the use of slow on-chip memories such as eFlash, off-chip memories, or core/bus ratios greater than 1.

Low Power RISCV CPU

SkyeChip

NEOX GA100 - RISC-V GPGPU for 3D graphics and AI at the edge

NEOX® | GA100 is the leading GPGPU solution for the MCU market and world's first GPGPU architecture based on RISC-V, offering the unique combination of performing both graphics and ΑΙ on th...

Raven - Full-chip reference implementation

Full-chip implementation of the PicoRV32 PicoSoC in X-Fab XH018. The raven chip contains two ADCs, a DAC, comparator, bandgap, RC oscillator, and over-temperature alarm, as well as 16 bits of general-purpose digital inputs/outputs.

RISC-V high performance CPU

Ventana s first generation RISC-V high performance CPU is targeted at data center, edge, and other general computing applications. The configurable CPU cluster can be integrated as IP within an SoC, d...

BI-350 - 32-bit RISC-V core with in-order pipeline

32-bit RISC-V core with in-order pipeline.Tiny Linux-capable processor for IoT applications.

E2 Series - Power & area optimized: 2-3-stage, single-issue pipeline, as small as 13.5k gates

The E2 Series is highly optimized for area and power while still offering class-leading performance. Targeted for microcontroller and embedded devices, the E2 Core can be configured to be as small as ...

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